INTERFACING DEVICES

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8255 PPI

8279 KEYBOARD/DISPLAY

8259 INTERRUPT CONTROLLER

8257 DMA CONTROLLER

8251 USART

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USART-8251(Universal Synchronous Asynchronous Receiver Transmitter)

USART-8251(Universal Synchronous Asynchronous Receiver Transmitter)

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data   communication. In a microprocessor system the CPU has to perform the data conversion like serial to parallel or parallel to serial and transmit the data to peripheral devices. This process will waste the precious time of the CPU. In order to release the CPU from this burden and continue its processing work, INTEL introduced a 28-pin DIP chip called the programmable communication interface. This chip will take care of all the communication activities and lessens the burden of the Microprocessor .This chip is compatible with all the INTEL processors. This 8251 receives parallel data from the CPU and transmits serial data after conversion. Similarly it also receives serial data from   outside devices and transmits parallel data into the CPU after conversion.

The Block diagram of 8251 is shown below the USART chip consists of four important sections .They are     

§ CPU Interface & Control Logic section

§ Transmitter Section

§ Receiver Section

§ Modem Control Section

.

CPU Interface & Control Logic section  :  The CPU interface and control logic accepts signals from  RD, WR, CLK, C/D, CS , D_7-0  and RESET pins of the system and generates the necessary signals for controlling the device operation. It consists of three registers, 8-bit data buffer register, one 16-bit control word register and one 8-bit status word register. The active low signals RD, WR, CS and C/D (Low) are used for read/write operations with these three registers.

When C/D bar is high, the control register is selected for writing control word or reading status word.  When C/D bar is low, the data buffer is selected for read/write operation. When the reset is high, it forces 8251A into the idle mode. The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section: The   transmitter section accepts parallel data from CPU and converts them into serial data. This section is  double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.

When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register. If buffer register is empty, then TxRDY is goes to high. If output register is empty then TxEMPTY goes to high. The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART. The clock frequency can be 1, 16 or 64 times the baud rate.

Receiver Section:  The receiver section accepts serial data and converts them into parallel data this   receiver section is also   double buffered with two registers.  i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data. When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again. If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register. The CPU reads the parallel data from the buffer register. When the input register loads a parallel data to buffer register, the RxRDY line goes high. The clock signal RxC (low) controls the rate at which bits are received by the USART. During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission. During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control Section: The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines. This unit takes care of handshake signals for MODEM interface. The Modem control signals are general purpose in nature and can be used for functions other than the Modem control if necessary. The Modem sends certain hand shake signals for proper communication between two devices. The DTR and RTS are the hand shake signals sent out by the 8251 to Modem and they are activated by using command instruction register. The DSR and CTS are the   hand shake signals sent by the Modem to 8251.

__

DSR (Data Set Ready): This signal is general purpose in nature. This signal is used to normally test the Modem condition. The CPU reads its condition by Status read operation.

___

DTR (Data Terminal ready): This is an output signal which is also a general purpose. The DTR signal is used to control the modem operation such as Data terminal ready or rate select. It can be set low by programming the appropriate bit in the command instruction word.

 ___

RTS (Request to Send): This output signal is normally used to control the Modem operations such as Request to send. This pin can be set low by programming the appropriate bit in the command instruction word.

___

CTS (Clear to Send): A low on this pin enables the 8251 to transmit the serial data, if the Tx EN bit in the command byte is set to one.

This Modem control section will decrease the burden of the CPU by converting the 0 s and 1s  into unique audio frequencies and transmit on the telephone network. 

Interfacing-devices

StudyPro: Programmable Interrupt Controller - 8259

StudyPro: Programmable Interrupt Controller - 8259

DMA Controller - Intel 8237/8257

DMA Controller - Intel 8237/8257

            In Direct Memory Access technique, the data transfer takes place without the intervention of CPU, so there must be a controller circuit which is programmable and which can perform the data transfer effectively.  For this purpose Intel introduced the controller chip 8257 which is known as DMA controller.  A DMA controller temporarily borrows the address bus, data bus and control bus from the microprocessor and transfers the data bytes directly from the port to memory devices.  As the transfer is handled totally by hardware, it is much faster than software program instructions.  A DMA controller can also transfer data from memory to a port.

Salient Features

            Intel 8257 is a programmable, 4-channel direct memory access controller i.e., four peripheral devices can request data transfer at any instant.  The request priorities are decided internally.  Each channel has two signals, DRQ (DMA Request) and (DMA acknowledge).  Each channel has two 16 bit registers.  One for the memory  address where the data transfer should being and the second for a 14-bit count.  There are also two 8-bit registers one is the mode set register and the other is status register.  It can operate both in slave and master mode.  It is a totally TTL compatible chip.

Block Diagram

      The functional block diagram is shown below.  It consists of

      ·    Data bus buffer

      ·    Read/Write logic

      ·    DMA channels

      ·    Control logic

      ·    Mode set Register

      ·    Status Register

Data Bus Buffer

            Three state bidirectional, 8 bit buffer interfaces the 8257 to the system data bus.  When the 8257 is being programmed by the CPU, eight bits of data for DMA address register, a terminal count register or the mode set register are received on the data bus.  When the CPU reads the DMA address register, a terminal count register or status register, the data is sent to the CPU over the data bus.

            When 8257 is operating as Master, during a DMA cycle, it gains control over the system buses.  In this mode, the 8257 sends out the 8 MSBs of the DMA address register of the channel being serviced on the D0-D7 pins at the starting of each DMA cycle to the 8212 latch.  After this, the bus is released to handle the memory data transfer during the remaining DMA cycle.

 Read/Write Logic

            In the slave mode, when the CPU reads data from or writes data to the 8257, the read/write logic accepts the I/OR (or) I/OW signals and decodes the least significant 4 address bits (A0 - A3).

            During DMA cycles, when 8257 is the master, the read/write logic generates the I/O read and memory write or I/O write and memory read signals which controls the data link with the peripheral that has been granted DMA cycle.  The different signals are

(I/O Read)

            It is active low bidirectional three-state line.  In the slave mode, it is an input, which allows the 8-bit status register or upper/lower byte of a 16 bit DMA address register of terminal count register to be read.  In the master mode,  is a control output, which is used to access data from a peripheral during the DMA write cycle.

 (I/O Write)

            It is an active low bi-directional tri-state line. In slave mode, it is an input, which allows microprocessor to write.  In the master mode,   is a control output, which allows data to be ouput in the peripheral during DMA read cycle.

CLK (Clock Input)

            This is the clock output of the microprocessor.

RESET

            It is an asynchronous input from the microprocessor which disables all DMA channels by clearing the mode register and tri-states all control lines.

A0 - A3 (Address Lines)

            These least significant four address lines are bidirectional.  In the slave mode they are inputs, which select one of the registers to be read or programmed.  In the master mode, they are outputs, which constitute the most significant 4 bits of the 16 bit memory address generated by the 8257.

(Chip Select)

            It is an active low input which enables the I/O read or I/O write input when the 8257 is being read or programmed in the slave mode.  In the master mode,   is automatically disabled to prevent the chip from selecting while performing the DMA function.

Control Logic Block

            This block controls the sequence operations during all DMA cycles by generating the appropriate control signals and 16 bit address that specifies the memory relations to be accessed.

A4 - A7 (Address Lines)

            These four address lines are tri-stated outputs which contains 4 to 7 of the 16 bit memory address generated by the 8257 during all DMA cycles.

READY

            This is an asynchronous input used to insert wait states during DMA read or write machine cycles.  Wait states are included between S3 and S4 states of the duty transfer.

HRQ (Hold Request)

            This output line requests the control of the system bus.  This is connected to the HOLD input of 8085.

DMA Channels

            The 8257 has four separate DMA channels each channel with two 16 bit registers (1) a DMA address register (2) Counter register. Both these registers must be initialized before a channel is enabled.  The DMA address register is loaded with the address of the first memory location to be accessed.  The value loaded into the low order 14 bits of the terminal count register specifies the number of DMA cycles minus one before the terminal count output is activated.

DRQ0 - DRQ3 (DMA Request)

            These are active low signals one for each of the four DMA channels.  The output acts as a chip select for the peripheral device requesting service.  The DACK line becomes 0 and then 1 for each byte of DMA data transfer.

Mode Set Register

            This register is used to set the mode of operation of 8257.  It is normally programmed by the CPU after the DMA address register and terminal count registers are initialized.  This register is cleared by RESET input, by disabling all options.  The mode set register is shown in Fig.  By setting the 4th bit we can opt for rotating priority.  Normally DRQ0 has highest priority and DRQ3 has lowest priority.  But in the rotating priority mode the priority of the channels has a circular sequence and after each DMA cycle, the priority of each channel changes.  If the rotating priority bit is reset, (is a zero) each DMA channel has a fixed priority in the fixed priority mode.  i.e., channel 0 has highest priority and channel-3 has lowest priority.

            The terminal count (TC) bits (bits 0 - 4) for the four channels are set when the Terminal Count output goes high for a channel.  The TC bits in the status word are cleared when the status word is read or when the 8257 receives a Reset input.  The update flag is cleared when (i) 8257 is reset or (ii) the auto load option is set in the mode set register or (iii) when the update cycle is completed.  The update flag is not affected by a status read operation.

DMA Working

In  8085 microprocessor two  lines dedicated for DMA operation.  They are HOLD and HLDA.  If any device  is in need of DMA service it activates a DRQ line.  Now the 8257 in turn sends out HOLD request (HRQ) to microprocessor on HOLD line.  The microprocessor then completes the current machine cycle and then goes to HOLD state, where the address bus, data bus and the related control bus signals are tri-stated.  Now the HLDA signal is activated.  The DMA controller which is a slave to the microprocessor so far will now become the master.  The DMA controller resolves the priorities of the requesting I/O devices and accordingly sends a signal to the suitable I/O device.

            When the microprocessor is the master, D7-0 is used by the 8257 for communication with microprocessor and A3-0 are i/p lines to 8257 to select register for communication with microprocessor.  But in the HOLD state the 8257 sends out most significant byte of memory address A15-8 on D7-0, sends out address information on A3-0 and also on A7-4.  Now   become output lines of 8257.  So, the 8257, after sending out a signal to the requesting I/O device, generates   and signals if it is a DMA read operation.  8257 generates and signals for DMA write operation.  Then a byte of data is transferred between I/O device and memory directly in 4 clock cycles.  This is known as a DMA machine cycle, at the end of which, the number of bytes to be transferred is decremented by 1 in the count register and address register is incremented by 1 to point to the next memory address for data transfer.

Interfacing-devices

Programmable Keyboard/Display Interface - 8279

Programmable  Keyboard/Display Interface - 8279

Intel 8279 is the programmable keyboard/display   controller, used to interface the keyboard and the display unit to the Microprocessors. The advantage of 8279 is that it is able to drive the signals for both the keyboard and display and hence it is possible for the microprocessor to concentrate on its processing tasks without wasting time.

The 8279 has two major sections. One is the Keyboard section and the other is the Display section. The 8279 chip provides four scan lines and eight return lines for interfacing keyboards and a set of eight output lines for interfacing a display.

The 8279  scans a keyboard regularly and detects a key depression ,de-bounces the signal from the pressed key and stores the code for the pressed key in an internal RAM  of size 8x8.The microprocessor reads this RAM  on first in first out basis. Similarly the 8279 refreshes the multiplexed display consisting of7-segment LED digits. The 7-segment codes for the data to be displayed are stored in a display RAM of size 16x8 with in the 8279.The 8279 automatically sends the code for each data to be displayed one after the other until all digits have been displayed.

The 8279 is available as a 40 pin DIP chip and it is compatible with all the INTEL basic processors. It works at +5 volts DC. The pin diagram of 8279 is shown below.

The keyboard section can interface to regular type-writer style keyboards or random toggle or thumb switches. The display section drives alphanumeric displays or a bank of indicator lights. So, the   CPU is relieved from scanning the keyboard or refreshing the display continuously. The keyboard portion can provide a scanned interface to a 64-contact key matrix. The keyboard portion interfaces an array of sensors or a strobed interface keyboard. Keyboard depressions can be 2-key lockout or N-key rollover. Keyboard entries are de-bounced and strobed in an 8-charcter FIFO. If more than 8 characters are entered, over-run status is set. Key entries set the interrupt output line to the   CPU.

The display section provides a scanned display interface for any display device. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279 has 16*8 displays RAM which can be organized into dual 16*4. The RAM can be loaded or interrogated by the CPU. Both  right entry, calculator and left entry typewriter display formats are possible. Both read and write of the display RAM can be done with auto-increment of the display RAM address.

Since the 8279 is directly connected to the microprocessor, the microprocessor can program all operating modes of 8279. The various input modes of the 8279 are  scanned keyboard, scanned sensor matrix and  strobed  input.

 BLOCK DIAGRAM : The block diagram of the 8279 is shown below and each block is explained.

I/O Control and Data Buffer

 The I/O control section controls the flow of data to/from the 8279. The data buffer interface the external bus of the system with internal bus of 8279.

 The pin Ao, RD and WR select the command, status or data read/write operations carried out by the CPU with 8279.

Control and Timing Register and Timing Control

These registers store the keyboard and display modes and other operating conditions programmed by CPU. The registers are written with Ao=1 and WR =0. The timing and control unit controls the basic timings for the operation of the circuit.

Scan Counter

Scan Counter divide down the operating frequency of 8279 to derive scan keyboard and scan display frequencies. The Scan Counter has two modes to scan the key matrix and refresh the display. In the Encoded mode, the counter provides a binary count that is to be externally decoded to provide the scan lines for keyboard and display (four externally decoded scan lines may drive up to 16 displays).In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3 (four internally decoded scan lines may drive up to 4 Displays). The Keyboard and Display both are in the same mode at a time.

Return Buffers and Keyboard Debounce and Control

Another set of functional components is return buffers and keyboard debounce and control. These components scan for a key closure row wise. If it is detected, the keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After the debounce period, if the key continues to be detected the code of the key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status.

FIFO/Sensor RAM and Status Logic

In Keyboard or strobed input mode, this block acts as 8-byte first-in-first-out (FIFO) RAM. Each key code of the pressed key is entered in the order of the entry, and in the meantime, read by the CPU, till the RAM becomes empty. The status logic generates an interrupt request after each FIFO read operation till the FIFO is empty. In scanned sensor matrix mode, this unit acts as sensor RAM. Each row of the sensor RAM is loaded with the status of the corresponding row of sensors in the matrix. If a sensor changes its state, the IRQ line goes high to interrupt the CPU.

Display Address Registers and Display RAM.

The Display address registers hold the addresses of the word currently being written or read by the CPU to or from the display RAM. The contents of the registers are automatically updated by 8279 to accept the next data entry by CPU. The 16-byte display RAM contains the 16-byte of data to be displayed on the sixteen 7-seg displays in the encoded scan mode

Interfacing-devices

Programmable Interrupt Controller - 8259

Programmable Interrupt Controller - 8259
Introduction

There is an absolute need of this Programmable Interrupt Controller for Interfacing 

I/O devices to the microprocessor The 8085 processor has 5 interrupt lines namely, Trap, 

RST 7.5, RST 6.5, RST 5.5 and INTR. So, we can interface five I/O devices, which can 

perform the interrupt driven data transfer safely. But, suppose we wish to connect more than 

five I/O devices, to the microprocessor, then we may have to connect more than one I/O 

device to the interrupt lines. This will affect the interrupt driven data transfer and the 

microprocessor has to perform polling. i.e, it has to check each device, which is in need of 

interrupt service. This polling has the dis-advantage of long time and slow interrupt 

response. Hence to overcome all these problems, INTEL introduced the 28 pin DIP chip -

8259. This device accepts interrupt requests from as many as 8 devices independently and as 

many as 64 I/O devices by cascading method.

Salient Features

INTEL 8259 is a single chip programmable interrupt controller which is compatible 

with 8085, 8086 and 8088 processors.

 It is a 28 pin DIP IC with N-MOS technology and requires a single +5 DC supply.

 It handles up to eight vectored priority interrupts for the CPU and cascaded for up to 

64 vectored priority interrupts without the need of any additional circuitry.

 when two 8259s are cascaded through cascade lines the first 8259 will act as master 

and the second 8259 will act as a slave.

Block Diagram

The block diagram of programmable interrupt controller is shown in Fig. below. The 

block diagram consists of eight sub units. They are Control logic, Read/write logic, Data bus 

buffer. Three register (IRR, ISR and IMR), 5 priority resolver and cascade buffer. The 

functions of each unit are explained below.

Priority Resolver

This logic unit determines the priorities of the bits set in the IRR. The highest priority 

is selected and strobed in to the corresponding bit of the ISR during pulse.

Interrupt Mask Register (IMR)

The IMR stores the bits which mask the interrupt lines. The IMR operates on the 

IRR. Masking of a higher priority input will not affect the interrupt request lines of lower 

priority.

Control Logic

This unit has two pins. INT (Interrupt) as an output pin and (interrupt acknowledge) 

as an input pin. The INT is connected to the interrupt pin of the microprocessor unit. 

Whenever an interrupt is noticed by the CPU, it generates signal.

Working of 8259

The 8259 accepts interrupt requests from any one of the 8 I/O lines (IR0

- IR7

). Then 

it ascertains the priority of the interrupt lines. Then it ascertains the priority of the interrupt 

lines. Suppose, the received interrupt has higher priority than currently serviced, it interrupts

the microprocessor and after receiving the interrupt acknowledgement from microprocessor. 

It provides a 3 byte CALL instruction. The sequence of steps that occur when an interrupt 

request line of 8259 goes high is as follows.

 The 8259 accepts the requests on IR0

- IR7

in IRR. Then it checks the contents of 

IMR whether that request is masked or not.

 The 8259, then checks ISR to know the interrupt levels that are being currently 

serviced. After this 8259 sends a high INT to 8085 processor. Normally, it is the job 

of the priority resolver to check the contents of IRR, IMR and ISR and decide whether 

to activate INT output of 8259 or not.

 Now 8085 processor responds by suspending the program flow at the end of the 

current instruction and makes low.

 On receiving, 8259 sends code for CALL to the microprocessor on D7-0

bus.

 This code for CALL in IR register of 8259 causes the 8085 to issue two more signals. 

When goes low the second time, 8259 places LSB of ISS address on the data bus. When 

goes low the third time, 8259 places the MSB of ISS address ont he data bus.

 Now, the microprocessor branches to the ISS after saving the contents of program 

counter on the stack top.

 After finishing the ISS, the control returns to the main program by popping the top of 

stack to PC.

Programming 8259

The 8259 requires two types of command words namely, Initialization Command 

Words (ICW) and Operational Command Words (OCW). The 8259 can be initialized with 

four ICWs, the first two are essential and the other two are optional based on the modes being 

used. These words must be issued in a sequence. Once the 8259 is initialized, the 8259 can 

operate in various modes by using three different OCWs.

Interfacing-devices

Control Word 8255

Control Word Format 8255

The 8255A has an 8 bit control register.  The contents of this register called, the control word, decides the I/O function for each port.  This register is not accessible for a read operation.

control word for I/O modes

 When D0 = 0,  port C Lower - output port

                        D0 = 1,  port C Lower - input port.

            The bit D1 configures port B as an 8 bit wide input or output

            When   D1 = 0,  port B is output port.

                        D1 = 1,  port B is input port.

            The bit D2 is the mode select bit for port B and the lower 4 bits of port C.

                        D2 = 0, selects Mode 0

                        D2 = 1, selects Mode 1.

            The bits D3 through D6 in the control register correspond to the group A control.

            Bits D3 and D4 of the control register are used to configure the operation of the upper half of port C and complete port A.

            When   D3 = 0,  port C upper is output port.

            or         D3 = 1,  port C upper is input port.

            Similarly when D4 = 0, port A is output port.

                              or   D4 = 1, port A is input port.

            The bits D5 and D6 are used to select among the three modes of operation names mode 0, mode 1 and mode 2.

                        D6 D5             = 00 selects mode 0

                                    = 01 selects mode 1

                                    = 1x selects mode 2.

            The last control register bit D7 is the mode set flag, which is shown in Fig.3.

                        D7       = 1 selects I/O mode and

                        D7       = 0 selects BSR mode.

BSR Mode Control Word Register Format

 The bit set/reset function is not really a control word.  Instead, it allows individual bits of port C to be set or reset.  But only one bit can be set or reset at a time.  One of the advantages of this mode is that individual bits of port C can be changed without changing any of the others.  This is needed when port C is used to control the ON/OFF status of several external devices.

            For example, the device connected to PC4 can be turned ON without affecting the status of any devices connected to the other seven outputs.

            The bit set/reset function is used in mode 1 and 2 to enable interrupt outputs available in these modes.

OPERATIONAL MODES OF 8255

OPERATIONAL MODES OF 8255

OPERATIONAL MODES OF 8255

8255 can be mainly configured in two modes.

                        i)  Input/Output mode (I/O mode)

                        ii)  Bit Set-Reset mode (BSR mode)

  Input/Output mode

            In I/O mode, the ports of 8255 acts as programmable ports, while in BSR mode only port C (PC0 - PC7) can be used to set or reset its individual port bits.

            The 8255 can programmed to operate in any one of the following modes.

            i) Mode 0 (simple mode)         ii)  Mode 1 (strobed mode)    

            iii) Mode 2 (bi-directional bus mode)

Mode 0: Simple I/O Mode

            This is a simple I/O or basic mode in which no hand shake signals are used.  Port A and Port B are used as two simple 8 bit I/O ports and port C as two 4 bit ports it is used with those I/O devices whose timing characteristics are clearly known.  For example, if an I/O device sends a byte for every 10 ms, to the UP, we can execute the IN instruction for every 10 ms to receive the data.

            All the 3 ports can be programmed in Mode 0.

Mode 1: Strobed Mode

            This is a handshake I/O mode (strobed mode) in which the data transfer is controlled by handshake signals.  For example, when the microprocessor wish to transfer the data to a relatively slow device like printer, for proper transfer of data handshake signals are used to inform the processor whether the printer is ready to receive the data or not.  The data transfer by handshake use both port A and port B as 8 bit input/output ports.  Port A uses the upper three signals PC3, PC4 and PC5 where as port B uses the lower signals PC2, PC1 and PC0 for handshaking signals.  The remaining two lines of port C are used in Mode 0.  The unique feature of this mode is that the data transfer can take place without direct CPU intervention.  When port A or port B are configured as input ports the three control signals used are IBF (Input Buffer Full),  (strobe) and INTR (Interrupt request).  Similarly when port A or port B are programmed as mode 1 output ports, the three control signals used are  (Output Buffer Full),  (Acknowledge) and INTR (Interrupt Request).

            A very important point to be remembered is that only port A and port B can be configured in mode 1.

 Mode 2: Bidirectional I/O (or) Strobed Bidirectional I/O

            In this mode port A alone can be configured to both, transmit and receive data.  Place over a single 8 bit data bus using handshaking signals.  This mode of operation is useful when transferring data between two computers.  As it is bidirectional I/O, it needs more number of handshake signals i.e., 5 lines of port C, PC3 - PC7.  The remaining lines of port C can be used by port B in Mode 1.  So, when port A is programmed to operate in mode 2, port B can operate in mode0 or mode1.If programmed for mode 0, PC0 - PC2 can be programmed as mode 0 inputs or outputs. If port B is programmed for mode 1, PC0 - PC2 become handshake signals for this port.

            In conclusion, we can understand that,

            Port A can be in Mode 0, Mode 1 or Mode 2.

            Port B can be in Mode 0 or Mode 1

            Port C can only be in Mode 0.

Note:  A high on reset line of 8255, resets all the ports A, B and C to work as input ports in mode 0. The reset pin of 8255 is generally connected to Reset Out pin of 8085.

 BSR (Bit Set/Reset) Mode

            The BSR mode is related to only with the 8 bits of port C, which can be set or reset by writing an appropriate control word in the control register.  A control word with bit D7 = 0 is treated as a BSR control word.  It does not change any previously transmitted control word with bit D7=1.So, the I/O operations of port A and port B are not changed by a BSR control word.  In BSR mode, individual bits of port C can be used for applications such as an ON/OFF switch.