Programmable Interrupt Controller - 8259

Programmable Interrupt Controller - 8259
Introduction

There is an absolute need of this Programmable Interrupt Controller for Interfacing 

I/O devices to the microprocessor The 8085 processor has 5 interrupt lines namely, Trap, 

RST 7.5, RST 6.5, RST 5.5 and INTR. So, we can interface five I/O devices, which can 

perform the interrupt driven data transfer safely. But, suppose we wish to connect more than 

five I/O devices, to the microprocessor, then we may have to connect more than one I/O 

device to the interrupt lines. This will affect the interrupt driven data transfer and the 

microprocessor has to perform polling. i.e, it has to check each device, which is in need of 

interrupt service. This polling has the dis-advantage of long time and slow interrupt 

response. Hence to overcome all these problems, INTEL introduced the 28 pin DIP chip -

8259. This device accepts interrupt requests from as many as 8 devices independently and as 

many as 64 I/O devices by cascading method.

Salient Features

INTEL 8259 is a single chip programmable interrupt controller which is compatible 

with 8085, 8086 and 8088 processors.

 It is a 28 pin DIP IC with N-MOS technology and requires a single +5 DC supply.

 It handles up to eight vectored priority interrupts for the CPU and cascaded for up to 

64 vectored priority interrupts without the need of any additional circuitry.

 when two 8259s are cascaded through cascade lines the first 8259 will act as master 

and the second 8259 will act as a slave.

Block Diagram

The block diagram of programmable interrupt controller is shown in Fig. below. The 

block diagram consists of eight sub units. They are Control logic, Read/write logic, Data bus 

buffer. Three register (IRR, ISR and IMR), 5 priority resolver and cascade buffer. The 

functions of each unit are explained below.

Priority Resolver

This logic unit determines the priorities of the bits set in the IRR. The highest priority 

is selected and strobed in to the corresponding bit of the ISR during pulse.

Interrupt Mask Register (IMR)

The IMR stores the bits which mask the interrupt lines. The IMR operates on the 

IRR. Masking of a higher priority input will not affect the interrupt request lines of lower 

priority.

Control Logic

This unit has two pins. INT (Interrupt) as an output pin and (interrupt acknowledge) 

as an input pin. The INT is connected to the interrupt pin of the microprocessor unit. 

Whenever an interrupt is noticed by the CPU, it generates signal.

Working of 8259

The 8259 accepts interrupt requests from any one of the 8 I/O lines (IR0

- IR7

). Then 

it ascertains the priority of the interrupt lines. Then it ascertains the priority of the interrupt 

lines. Suppose, the received interrupt has higher priority than currently serviced, it interrupts

the microprocessor and after receiving the interrupt acknowledgement from microprocessor. 

It provides a 3 byte CALL instruction. The sequence of steps that occur when an interrupt 

request line of 8259 goes high is as follows.

 The 8259 accepts the requests on IR0

- IR7

in IRR. Then it checks the contents of 

IMR whether that request is masked or not.

 The 8259, then checks ISR to know the interrupt levels that are being currently 

serviced. After this 8259 sends a high INT to 8085 processor. Normally, it is the job 

of the priority resolver to check the contents of IRR, IMR and ISR and decide whether 

to activate INT output of 8259 or not.

 Now 8085 processor responds by suspending the program flow at the end of the 

current instruction and makes low.

 On receiving, 8259 sends code for CALL to the microprocessor on D7-0

bus.

 This code for CALL in IR register of 8259 causes the 8085 to issue two more signals. 

When goes low the second time, 8259 places LSB of ISS address on the data bus. When 

goes low the third time, 8259 places the MSB of ISS address ont he data bus.

 Now, the microprocessor branches to the ISS after saving the contents of program 

counter on the stack top.

 After finishing the ISS, the control returns to the main program by popping the top of 

stack to PC.

Programming 8259

The 8259 requires two types of command words namely, Initialization Command 

Words (ICW) and Operational Command Words (OCW). The 8259 can be initialized with 

four ICWs, the first two are essential and the other two are optional based on the modes being 

used. These words must be issued in a sequence. Once the 8259 is initialized, the 8259 can 

operate in various modes by using three different OCWs.

Interfacing-devices