Programmable Keyboard/Display Interface - 8279

Programmable  Keyboard/Display Interface - 8279

Intel 8279 is the programmable keyboard/display   controller, used to interface the keyboard and the display unit to the Microprocessors. The advantage of 8279 is that it is able to drive the signals for both the keyboard and display and hence it is possible for the microprocessor to concentrate on its processing tasks without wasting time.

The 8279 has two major sections. One is the Keyboard section and the other is the Display section. The 8279 chip provides four scan lines and eight return lines for interfacing keyboards and a set of eight output lines for interfacing a display.

The 8279  scans a keyboard regularly and detects a key depression ,de-bounces the signal from the pressed key and stores the code for the pressed key in an internal RAM  of size 8x8.The microprocessor reads this RAM  on first in first out basis. Similarly the 8279 refreshes the multiplexed display consisting of7-segment LED digits. The 7-segment codes for the data to be displayed are stored in a display RAM of size 16x8 with in the 8279.The 8279 automatically sends the code for each data to be displayed one after the other until all digits have been displayed.

The 8279 is available as a 40 pin DIP chip and it is compatible with all the INTEL basic processors. It works at +5 volts DC. The pin diagram of 8279 is shown below.

The keyboard section can interface to regular type-writer style keyboards or random toggle or thumb switches. The display section drives alphanumeric displays or a bank of indicator lights. So, the   CPU is relieved from scanning the keyboard or refreshing the display continuously. The keyboard portion can provide a scanned interface to a 64-contact key matrix. The keyboard portion interfaces an array of sensors or a strobed interface keyboard. Keyboard depressions can be 2-key lockout or N-key rollover. Keyboard entries are de-bounced and strobed in an 8-charcter FIFO. If more than 8 characters are entered, over-run status is set. Key entries set the interrupt output line to the   CPU.

The display section provides a scanned display interface for any display device. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279 has 16*8 displays RAM which can be organized into dual 16*4. The RAM can be loaded or interrogated by the CPU. Both  right entry, calculator and left entry typewriter display formats are possible. Both read and write of the display RAM can be done with auto-increment of the display RAM address.

Since the 8279 is directly connected to the microprocessor, the microprocessor can program all operating modes of 8279. The various input modes of the 8279 are  scanned keyboard, scanned sensor matrix and  strobed  input.

 BLOCK DIAGRAM : The block diagram of the 8279 is shown below and each block is explained.

I/O Control and Data Buffer

 The I/O control section controls the flow of data to/from the 8279. The data buffer interface the external bus of the system with internal bus of 8279.

 The pin Ao, RD and WR select the command, status or data read/write operations carried out by the CPU with 8279.

Control and Timing Register and Timing Control

These registers store the keyboard and display modes and other operating conditions programmed by CPU. The registers are written with Ao=1 and WR =0. The timing and control unit controls the basic timings for the operation of the circuit.

Scan Counter

Scan Counter divide down the operating frequency of 8279 to derive scan keyboard and scan display frequencies. The Scan Counter has two modes to scan the key matrix and refresh the display. In the Encoded mode, the counter provides a binary count that is to be externally decoded to provide the scan lines for keyboard and display (four externally decoded scan lines may drive up to 16 displays).In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-SL3 (four internally decoded scan lines may drive up to 4 Displays). The Keyboard and Display both are in the same mode at a time.

Return Buffers and Keyboard Debounce and Control

Another set of functional components is return buffers and keyboard debounce and control. These components scan for a key closure row wise. If it is detected, the keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After the debounce period, if the key continues to be detected the code of the key is directly transferred to the sensor RAM along with SHIFT and CONTROL key status.

FIFO/Sensor RAM and Status Logic

In Keyboard or strobed input mode, this block acts as 8-byte first-in-first-out (FIFO) RAM. Each key code of the pressed key is entered in the order of the entry, and in the meantime, read by the CPU, till the RAM becomes empty. The status logic generates an interrupt request after each FIFO read operation till the FIFO is empty. In scanned sensor matrix mode, this unit acts as sensor RAM. Each row of the sensor RAM is loaded with the status of the corresponding row of sensors in the matrix. If a sensor changes its state, the IRQ line goes high to interrupt the CPU.

Display Address Registers and Display RAM.

The Display address registers hold the addresses of the word currently being written or read by the CPU to or from the display RAM. The contents of the registers are automatically updated by 8279 to accept the next data entry by CPU. The 16-byte display RAM contains the 16-byte of data to be displayed on the sixteen 7-seg displays in the encoded scan mode

Interfacing-devices