DMA Controller - Intel 8237/8257

DMA Controller - Intel 8237/8257

            In Direct Memory Access technique, the data transfer takes place without the intervention of CPU, so there must be a controller circuit which is programmable and which can perform the data transfer effectively.  For this purpose Intel introduced the controller chip 8257 which is known as DMA controller.  A DMA controller temporarily borrows the address bus, data bus and control bus from the microprocessor and transfers the data bytes directly from the port to memory devices.  As the transfer is handled totally by hardware, it is much faster than software program instructions.  A DMA controller can also transfer data from memory to a port.

Salient Features

            Intel 8257 is a programmable, 4-channel direct memory access controller i.e., four peripheral devices can request data transfer at any instant.  The request priorities are decided internally.  Each channel has two signals, DRQ (DMA Request) and (DMA acknowledge).  Each channel has two 16 bit registers.  One for the memory  address where the data transfer should being and the second for a 14-bit count.  There are also two 8-bit registers one is the mode set register and the other is status register.  It can operate both in slave and master mode.  It is a totally TTL compatible chip.

Block Diagram

      The functional block diagram is shown below.  It consists of

      ·    Data bus buffer

      ·    Read/Write logic

      ·    DMA channels

      ·    Control logic

      ·    Mode set Register

      ·    Status Register

Data Bus Buffer

            Three state bidirectional, 8 bit buffer interfaces the 8257 to the system data bus.  When the 8257 is being programmed by the CPU, eight bits of data for DMA address register, a terminal count register or the mode set register are received on the data bus.  When the CPU reads the DMA address register, a terminal count register or status register, the data is sent to the CPU over the data bus.

            When 8257 is operating as Master, during a DMA cycle, it gains control over the system buses.  In this mode, the 8257 sends out the 8 MSBs of the DMA address register of the channel being serviced on the D0-D7 pins at the starting of each DMA cycle to the 8212 latch.  After this, the bus is released to handle the memory data transfer during the remaining DMA cycle.

 Read/Write Logic

            In the slave mode, when the CPU reads data from or writes data to the 8257, the read/write logic accepts the I/OR (or) I/OW signals and decodes the least significant 4 address bits (A0 - A3).

            During DMA cycles, when 8257 is the master, the read/write logic generates the I/O read and memory write or I/O write and memory read signals which controls the data link with the peripheral that has been granted DMA cycle.  The different signals are

(I/O Read)

            It is active low bidirectional three-state line.  In the slave mode, it is an input, which allows the 8-bit status register or upper/lower byte of a 16 bit DMA address register of terminal count register to be read.  In the master mode,  is a control output, which is used to access data from a peripheral during the DMA write cycle.

 (I/O Write)

            It is an active low bi-directional tri-state line. In slave mode, it is an input, which allows microprocessor to write.  In the master mode,   is a control output, which allows data to be ouput in the peripheral during DMA read cycle.

CLK (Clock Input)

            This is the clock output of the microprocessor.

RESET

            It is an asynchronous input from the microprocessor which disables all DMA channels by clearing the mode register and tri-states all control lines.

A0 - A3 (Address Lines)

            These least significant four address lines are bidirectional.  In the slave mode they are inputs, which select one of the registers to be read or programmed.  In the master mode, they are outputs, which constitute the most significant 4 bits of the 16 bit memory address generated by the 8257.

(Chip Select)

            It is an active low input which enables the I/O read or I/O write input when the 8257 is being read or programmed in the slave mode.  In the master mode,   is automatically disabled to prevent the chip from selecting while performing the DMA function.

Control Logic Block

            This block controls the sequence operations during all DMA cycles by generating the appropriate control signals and 16 bit address that specifies the memory relations to be accessed.

A4 - A7 (Address Lines)

            These four address lines are tri-stated outputs which contains 4 to 7 of the 16 bit memory address generated by the 8257 during all DMA cycles.

READY

            This is an asynchronous input used to insert wait states during DMA read or write machine cycles.  Wait states are included between S3 and S4 states of the duty transfer.

HRQ (Hold Request)

            This output line requests the control of the system bus.  This is connected to the HOLD input of 8085.

DMA Channels

            The 8257 has four separate DMA channels each channel with two 16 bit registers (1) a DMA address register (2) Counter register. Both these registers must be initialized before a channel is enabled.  The DMA address register is loaded with the address of the first memory location to be accessed.  The value loaded into the low order 14 bits of the terminal count register specifies the number of DMA cycles minus one before the terminal count output is activated.

DRQ0 - DRQ3 (DMA Request)

            These are active low signals one for each of the four DMA channels.  The output acts as a chip select for the peripheral device requesting service.  The DACK line becomes 0 and then 1 for each byte of DMA data transfer.

Mode Set Register

            This register is used to set the mode of operation of 8257.  It is normally programmed by the CPU after the DMA address register and terminal count registers are initialized.  This register is cleared by RESET input, by disabling all options.  The mode set register is shown in Fig.  By setting the 4th bit we can opt for rotating priority.  Normally DRQ0 has highest priority and DRQ3 has lowest priority.  But in the rotating priority mode the priority of the channels has a circular sequence and after each DMA cycle, the priority of each channel changes.  If the rotating priority bit is reset, (is a zero) each DMA channel has a fixed priority in the fixed priority mode.  i.e., channel 0 has highest priority and channel-3 has lowest priority.

            The terminal count (TC) bits (bits 0 - 4) for the four channels are set when the Terminal Count output goes high for a channel.  The TC bits in the status word are cleared when the status word is read or when the 8257 receives a Reset input.  The update flag is cleared when (i) 8257 is reset or (ii) the auto load option is set in the mode set register or (iii) when the update cycle is completed.  The update flag is not affected by a status read operation.

DMA Working

In  8085 microprocessor two  lines dedicated for DMA operation.  They are HOLD and HLDA.  If any device  is in need of DMA service it activates a DRQ line.  Now the 8257 in turn sends out HOLD request (HRQ) to microprocessor on HOLD line.  The microprocessor then completes the current machine cycle and then goes to HOLD state, where the address bus, data bus and the related control bus signals are tri-stated.  Now the HLDA signal is activated.  The DMA controller which is a slave to the microprocessor so far will now become the master.  The DMA controller resolves the priorities of the requesting I/O devices and accordingly sends a signal to the suitable I/O device.

            When the microprocessor is the master, D7-0 is used by the 8257 for communication with microprocessor and A3-0 are i/p lines to 8257 to select register for communication with microprocessor.  But in the HOLD state the 8257 sends out most significant byte of memory address A15-8 on D7-0, sends out address information on A3-0 and also on A7-4.  Now   become output lines of 8257.  So, the 8257, after sending out a signal to the requesting I/O device, generates   and signals if it is a DMA read operation.  8257 generates and signals for DMA write operation.  Then a byte of data is transferred between I/O device and memory directly in 4 clock cycles.  This is known as a DMA machine cycle, at the end of which, the number of bytes to be transferred is decremented by 1 in the count register and address register is incremented by 1 to point to the next memory address for data transfer.

Interfacing-devices