USART-8251(Universal Synchronous Asynchronous Receiver Transmitter)

USART-8251(Universal Synchronous Asynchronous Receiver Transmitter)

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data   communication. In a microprocessor system the CPU has to perform the data conversion like serial to parallel or parallel to serial and transmit the data to peripheral devices. This process will waste the precious time of the CPU. In order to release the CPU from this burden and continue its processing work, INTEL introduced a 28-pin DIP chip called the programmable communication interface. This chip will take care of all the communication activities and lessens the burden of the Microprocessor .This chip is compatible with all the INTEL processors. This 8251 receives parallel data from the CPU and transmits serial data after conversion. Similarly it also receives serial data from   outside devices and transmits parallel data into the CPU after conversion.

The Block diagram of 8251 is shown below the USART chip consists of four important sections .They are     

§ CPU Interface & Control Logic section

§ Transmitter Section

§ Receiver Section

§ Modem Control Section

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CPU Interface & Control Logic section  :  The CPU interface and control logic accepts signals from  RD, WR, CLK, C/D, CS , D_7-0  and RESET pins of the system and generates the necessary signals for controlling the device operation. It consists of three registers, 8-bit data buffer register, one 16-bit control word register and one 8-bit status word register. The active low signals RD, WR, CS and C/D (Low) are used for read/write operations with these three registers.

When C/D bar is high, the control register is selected for writing control word or reading status word.  When C/D bar is low, the data buffer is selected for read/write operation. When the reset is high, it forces 8251A into the idle mode. The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section: The   transmitter section accepts parallel data from CPU and converts them into serial data. This section is  double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.

When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register. If buffer register is empty, then TxRDY is goes to high. If output register is empty then TxEMPTY goes to high. The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART. The clock frequency can be 1, 16 or 64 times the baud rate.

Receiver Section:  The receiver section accepts serial data and converts them into parallel data this   receiver section is also   double buffered with two registers.  i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data. When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again. If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register. The CPU reads the parallel data from the buffer register. When the input register loads a parallel data to buffer register, the RxRDY line goes high. The clock signal RxC (low) controls the rate at which bits are received by the USART. During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission. During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control Section: The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines. This unit takes care of handshake signals for MODEM interface. The Modem control signals are general purpose in nature and can be used for functions other than the Modem control if necessary. The Modem sends certain hand shake signals for proper communication between two devices. The DTR and RTS are the hand shake signals sent out by the 8251 to Modem and they are activated by using command instruction register. The DSR and CTS are the   hand shake signals sent by the Modem to 8251.

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DSR (Data Set Ready): This signal is general purpose in nature. This signal is used to normally test the Modem condition. The CPU reads its condition by Status read operation.

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DTR (Data Terminal ready): This is an output signal which is also a general purpose. The DTR signal is used to control the modem operation such as Data terminal ready or rate select. It can be set low by programming the appropriate bit in the command instruction word.

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RTS (Request to Send): This output signal is normally used to control the Modem operations such as Request to send. This pin can be set low by programming the appropriate bit in the command instruction word.

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CTS (Clear to Send): A low on this pin enables the 8251 to transmit the serial data, if the Tx EN bit in the command byte is set to one.

This Modem control section will decrease the burden of the CPU by converting the 0 s and 1s  into unique audio frequencies and transmit on the telephone network. 

Interfacing-devices