PROGRAMMABLE PERIPHERAL INTERFACE - 8255

---------------------PROGRAMMABLE PERIPHERAL INTERFACE -  8255A

 INTEL introduced this programmable peripheral interface (PPI) chip 8255A for interfacing peripheral devices to the 8085 system. This versatile chip 8255A is used as a general purpose peripheral device for parallel data transfer between microprocessor and a peripheral device by interfacing the device to the system data bus.  The PPI has three programmable I/O ports viz., Port A, Port B and Port C each of 8 bit width.  Port C can be treated as two ports – Port C upper (PC7-4) and Port lower (PC3 – 0) and these two can be independently programmed as INPUT or OUTPUT ports also.

Salient Features

i.    It is a general purpose programmable I/O device which is compatible with all INTEL processors and also most other processors.

ii.   It provides 24 I/O pins which may be individually programmed in two groups.

iii.  This chip is also completely TTL compatible.

iv.  It is available in 40 pin DIP and 44 pin plastic leaded chip carrier (PLCC) packages.

v.   It has three 8 bit ports.  Port A, Port B and Port C.  Port C is treated as two 4 bit ports also.

vi.  This 8255 is mainly programmed in two modes (a) the I/O mode and (b) The bit set/reset mode  (BSR) mode.  The I/O mode is further divided into three modes: Mode 0, Mode 1, and Mode 2.

vii. An 8 bit control resister is used to configure the modes of 8255.

There is also another 8 bit port called control port, which decides the configuration of 8255 ports.  This port is written by the microprocessor only. 

Functional Block Diagram of 8255A Programmable Peripheral Interface (PPI)

Data Bus buffer

            This tri-state bidirectional 8 bit buffer is used to interface the data bus of 8255A to the system data bus.  Data is transmitted or received by the buffer when the CPU executes input or output instructions control words and status information is also transferred through the data bus buffer.

Read/Write and Control Logic

            The function of this block is to manage all the internal and external transfers of both data and control or status words.  It accepts inputs from the CPU and inturn issues commands to both of the control groups.

Group A and Group B Controls

            Each of the group A and group B control blocks receives control words from the CPU and issues suitable commands to the ports associated to it.  The group A control block controls port A and port C Upper (PC7 - PC4) where are group B control block, controls port B and port C lower (PC3 - PC0)

Port A

            It has one 8 bit data output latch/buffer and one 8 bit input latch buffer.  This port A can be configured in all the three modes: mode0, mode 1, mode 2.

Port B

            This has an 8 bit data input/output latch/ buffer which can be programmed both in mode 0 and mode 1.

Port C

            It has one 8 bit unlatched input buffer and an 8 bit output latch/buffer.  This port can be divided into two 4 bit ports under the mode control.  These two ports can be used as control signals for ports A and B in the handshake mode.

Control Word 8255
OPERATIONAL MODES OF 8255
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