Instruction pipelining in 8086
A
technique used in advanced microprocessors where
the microprocessor begins executing a
second instruction before
the first has been completed. That is, several instructions are in the pipeline simultaneously, each at a different
processing stage. Instruction queue in the BIU handles the pipelining in 8086.
During cycle 1 there is only one operation during cycle 2 the processor goes to decoding stage of first instruction and the buses will be used to fetch the next instruction ie instruction 2 during cycle 3 we can see that 3 process are performed by the processor this increases the execution time.
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